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Senior Member Technical Staff SW Deveolper > Mass [02/12/2010] |
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Position Description
This is a position for development of SystemVerilog simulation extensions to the IES. A candidate for this position will write specifications, code implementation, and perform unit level testing of SystemVerilog construct and features in the IES. It is expected that individuals in this role will have the ability to specify tasks and work with senior IUS engineers to deliver quality code to the IUS coding standards. Product support is an expectation for this role. Position Requirements
Candidates must have a strong background in C/C++ and an understanding of modern coding practices including Clearcase source control system. Candidates will benefit from a knowledge of HDLs (Verilog & VHDL), SystemVerilog and e knowledge and their application in advanced verification. Company Information
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Job Type: Permanent Location: Massachusetts-Boston South
Salary: [n/a] Date available: asap Specialist Industry: Software Engineering Industry Job Contact:: Contact Tel:: Interview Dates:: Closing Date:: Salary-Pay Range:: Minimum Experience:: 3 - 5 Years Software and Commercial Skills Company: Cadence Design Systems Inc Company Description: [n/a] Company Website: [n/a]
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05/16/2012